The present invention relates to a method for separately measuring capacitive components in a semiconductor device and a Test Element Group (TEG) pattern having its function.
In the design and development of high-performance LSIs, it is significant to sample (measure) the characteristics of semiconductor elements placed in an LSI with high accuracy, and a technique for sampling (measuring) the same and the optimal design of a TEG are required.
In recent years, as semiconductor elements become finer, the influences of noises caused by crosstalk and the degradation of delay characteristics due to a Miller capacitance have become more obvious. Therefore, it has been required to sample capacitive components of individual conductor members, such as interconnects and semiconductor layers, of the characteristics of the semiconductor device with high accuracy.
A technique for sampling parasitic capacitances as disclosed in Patent Document 1 (U.S. Pat. No. 6,300,765 B1) has been conventionally known. The objective of this technique is to separately measure interconnect-to-interconnect capacitances C12 and C13.
FIG. 7 is a circuit diagram illustrating the structure of a capacitance measuring circuit for measuring parasitic capacitances as disclosed in Patent Document 1.
As shown in this figure, a P-type Metal Insulator Semiconductor Field Effect Transistor (PMISFET) 101 and an N-type Metal Insulator Semiconductor Field Effect Transistor) 102 are connected in series to each other, and the drain of each of the PMISFET 101 and the NMISFET 102 is connected via a node N1 to an interconnect W1. The source of the PMISFET 101 is connected to a power supply pad PST for supplying a power supply voltage Vdd, while the source of the NMISFET 102 is connected to a ground pad GND (voltage Vss). The gate of the PMISFET 101 is connected to a charging pad 111, while the gate of the NMISFET 102 is connected to a discharging pad 112. Furthermore, there are provided an interconnect W2 arranged in a layer higher than the interconnect W1 and crossing the interconnect W1 when viewed in a plane, and an interconnect W3 extending substantially parallel to the interconnect W1 and crossing the interconnect W2 when viewed in the same plane. The interconnect W2 is connected to a first pad 113 for measuring current via a node N2 and an NMISFET 103, while the interconnect W3 is connected to a second pad 114 for measuring current via a node N3 and an NMISFET 104. The gate of each of the NMISFETs 103 and 104 is connected to a current-monitoring pad 115. The capacitance measuring circuit is configured so that it can measure currents I1 and I2 by bringing the first and second pads 113 and 114 for measuring current into contact with probes of ammeters 121 and 122, respectively. When the probes of the ammeters 121 and 122 come into contact with the pads 113 and 114 for measuring current, respectively, the sources of the NMISFETs 103 and 104 are fixed at 0V.
The interconnect W2 is connected via an NMISFET 105 to the ground pad GND, while the interconnect W3 is connected via an NMISFET 106 to the ground pad GND.
Here, the capacitance between the interconnects W1 and W2 is designated C12, the capacitance between the interconnects W1 and W3 is designated C13, and the capacitance between the interconnects W2 and W3 is designated C23. In this relation, the capacitance C12 is a value obtained by dividing a charge induced in the interconnect W2 when a voltage is applied to the interconnect W1, by the applied voltage. The capacitance C13 is a value obtained by dividing a charge induced in the interconnect W3 when a voltage is applied to the interconnect W1, by the applied voltage.
FIG. 8 is a timing diagram illustrating the operation of the capacitance measuring circuit shown in FIG. 7. The known capacitance measuring circuit operation will be described with reference to FIG. 8.
First, the power supply voltage Vdd is fixed at a voltage Vcc, while the ground voltage Vss is fixed at 0V. A charging voltage V111 and a discharging voltage V112 are switched between the voltages Vcc and Vss such that both of the PMISFET 101 and the NMISFET 102 are not ON at any timing. However, there exists a timing at which both of the PMISFET 101 and the NMISFET 102 are OFF. Therefore, no flow-through current passing through both of the PMISFET 101 and the NMISFET 102 is produced.
Between timings t0 and t1, the discharging voltage V112 is held at the voltage Vcc so that the NMISFETs 102, 105 and 106 are ON. Therefore, the potentials of the nodes N1, N2 and N3 are fixed at the ground voltage Vss.
Between timings t1 and t2, all the MISFETs 101, 102, 103, 104, 105, and 106 are OFF.
Between timings t2 and t3, since the PMISFET 101 and the NMISFET 102 are OFF, and the NMISFETs 103 and 104 are ON, it is possible to monitor currents.
Between timings t3 and t4, since the PMISFET 101 is ON, a charge from the interconnect W1 to the interconnects W2 and W3 is induced. At this time, currents are monitored using the ammeters 121 and 122, thereby measuring the capacitances C12, C13 and C23. The time between the timings t3 and t4 is set at a time enough to induce a charge in the interconnect W1 and monitor the currents using the ammeters 121 and 122.
Between timings t4 and t5, the PMISFET 101 is OFF.
Between timings t5 and t6, since all the MISFETs are OFF, it becomes impossible to monitor the currents.
Between timings t6 and t7, the same operations as between the timings t0 and t1 are carried out. Thereafter, the above-mentioned operations for the timings t1 through t7 are periodically repeated.
The value to be observed by a measuring device using this circuit is a mean value between the currents I1 and I2 detected over time by the ammeters 121 and 122, respectively. When the frequency of the gate input waveform is f(=1/T) (T denotes the time from the timing t0 to the timing t7), the following formulae (1) and (2) hold:I1=C12·Vcc·f  (1)I2=C13·Vcc·f  (2)
By using the formulae (1) and (2), measured capacitance values C12 and C13 are obtained from the following formulae (3) and (4):C12=I1/(Vcc·f)  (3)C13=I2/(Vcc·f)  (4)
This known technique is characterized in that the desired capacitances C12 and C13 can directly be measured without the need for canceling the parasitic capacitance of a transistor.